1. Field
Certain embodiments of the present disclosure generally relate to asynchronous interconnects and, more particularly, to designing circuit blocks and handshaking protocol for an asynchronous network.
2. Background
Large-scale system on chip applications that use a global synchronous interconnect with a high-frequency clock may suffer from serious clock skew issues. Incorporating multiple clock domains in such synchronous systems may be difficult. An asynchronous network bus may be preferred for such high performance or large-scale applications.